Integrated circuits often include logic devices that receive input signals and provide output signals responsive to the input signals. Output signals from logic devices are often used as input signals to subsequent logic devices. As a result, the output signals often need to have sufficient voltage and current to drive the subsequent logic devices. A common practice is to buffer the output signals using transistors to ensure adequate output signal strength. However, providing each output signal with its own buffer and driver, supplied by a power supply, can create noise problems when many output signals switch state at the same time.
One solution to this problem has involved controlling the slew rate of the output buffers. Slew rate generally refers to the speed at which a voltage or current changes. Controlling the slew rate allows a designer of an integrated circuit to slow the speed of the integrated circuit by driving the output buffers with less current.
FIG. 1 illustrates a typical integrator-based slew rate control circuit 100. In this example, the slew rate control circuit 100 includes a driver circuit 102 and an integrator 104. The driver circuit 102 includes a P-channel Metal Oxide Semiconductor (MOS) transistor 106 and an N-channel MOS transistor 108. The transistors 106 and 108 represent pull-up and pull-down transistors, respectively. Gate terminals of the transistors 106 and 108 are coupled to an input signal 110. A voltage of the input signal 110 is referred to as an input voltage VIN. A drain terminal of the transistor 106 and a drain terminal of the transistor 108 are coupled to the integrator 104. A source terminal of the transistor 106 is coupled to a power supply voltage 112 via a current source 114, and a source terminal of the transistor 108 is grounded via a current source 116. The integrator 104 includes an operational amplifier (“op-amp”) 118 and a capacitor 120 coupled to an inverting input and an output of the op-amp 118. The op-amp 118 generates an output signal 122. A voltage of the output signal 122 is referred to as an output voltage VOUT. A non-inverting input of the op-amp 118 receives a reference voltage VREF. An electrical interconnection 124 couples an output of the driver circuit 102 and the inverting input of the op-amp 118. A voltage on the interconnection 124 is referred to as an interconnection voltage VINT.
The interconnection voltage VINT may typically swing either to the power supply voltage 112 or to ground when an integration performed by the integrator 104 is complete. When another integration begins, there is typically a need to wait for the interconnection voltage VINT to swing close to the reference voltage VREF before any effective integration can occur. This period of time is referred to as “recovery time.” The recovery time typically depends directly on the size of the capacitor 120 and the charge/discharge currents from the current sources 114-116. This recovery time often causes a propagation delay between the input signal 110 received by the driver circuit 102 and the corresponding output signal 122 produced by the integrator 104.
FIG. 2 represents a circuit simulation that illustrates this delay between the input signal 110 and the output signal 122. The simulation involves the following parameters: the capacitor 120 has a capacitance of 2 pF, and the current sources 114-116 produce currents of 30 μA each. The main objective was to achieve a rise/fall time in the output signal 122 of 150 ns. As shown in FIG. 2, the delay time is approximately 100 ns. This amount of delay could be unreasonable or undesirable in certain circumstances.
To reduce the recovery time of the integrator 104, one solution has been to limit the interconnection voltage VINT so that it is as close to the reference voltage VREF as possible while still being sufficient to force a level change in the output voltage VOUT. This may reduce the signal swing on the interconnection 124. One technique to implement this solution has employed a voltage clamp 126 as shown in FIG. 3. FIG. 4 illustrates a previous implementation of the voltage clamp 126. As shown in FIG. 4, this implementation has two fixed biasing levels CBIAS_N and CBIAS_P. When the interconnection voltage VINT (124) is one threshold voltage below CBIAS_N, a transistor 128 turns on and limits the interconnection voltage VINT (124) from dropping further. When the interconnection voltage VINT (124) is one threshold voltage above CBIAS_P, a transistor 130 turns on and limits the interconnection voltage VINT (124) from rising further. However, this implementation typically has large variations in clamping levels due to process and temperature variations in the threshold voltage, resulting in a large variation in the recovery time.